Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience: 2 - 4 Years. Skills Expected: Strong Verilog, SVA and Formal environment development skills with working knowledge of any High Speed Interface protocols like AMBA/USB/PCIe/CXL/UCIe/UALink/Ethernet. Having experience in Formal Verification is mandatory. Develop detailed formal verification test plans based on design specifications and collaborate with design teams. Should have signed off multiple RTL blocks using Formal Verification. Having experience in complexity handling and deep bug hunting techniques preferable. We’re doing work that matters. Help us solve what others can’t.